In high-speed electronics, often current mode logic (CML) is employed instead of the widely used CMOS logic. Using CML circuits, the speed limiting factor of CMOS can be circumvented.

The speed limitation of standard CMOS technology is illustrated using an inverter.

The propagation delay through an inverter is given by

where ΔV_in is the input voltage swing, C_ds,p the drain-source capacitance of the p-MOS transistor and i_d,n the drain current of the n-MOS transistor. In order to reduce t_d, C_ds,p must be decrease and the current i_d,n should be increase. Dependences of C_ds,p and i_d,n on the transistor dimensions:

This means that reducing the gate length, i.e. moving to more advanced technologies, will reduce the delay through a logic gate. For a given technology, the gate width W_p of the p-MOS transistor must be reduced by simultaneously, increasing the gate width W_n of the n-MOS transistor. However, in CMOS logic, the gate width of the n- and p-MOS transistors are in strong relation (W_p=3•W_n since µ_n=3•µ_p) in order to set the switching level of the logic gate at a constant value, which is at V_DD/2.

For a given technology, the intrinsic delay of a CMOS gate can not be improved

Another circuit topology must be found. The basic idea is to decouple the dimensions of the charging current and the switch transistor.

The current I_charge charging the load is set by a current source (mirror) independently of the dimensions of the switch transistor (W_n, L_n). To reduce the propagation delay, I_charge is increased and W_n is decreased which reduces the parasitic capacitances. Of course, there are some lower limits for W_n and upper limits for I_charge, but the situation is much more relaxed.

• Voltage gain: g_m,n(W_n)•R_load>1
• Saturation: V_ds,sat<V_DD-V_cm-V_load

In current mode logic the differential version is used because of the numerous advantages.

Using current mode logic, the speed performance of logic circuits can be enhanced for a given transistor technology. The circuit designer has got more freedom to determine the circuit parameters and can therefore better optimize the circuits with respect to speed and power consumption.

Contact : Dr. Alex Huber, IME