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    Clock and Data Recovery

    There are different approaches to recover the data and the clock from a noisy and jittery serial input data stream. The classical clock data recovery (CDR) systems compare the phase and frequency of the incoming data signal (Rx DataIn) with the internally generated clock (Rx Clock) signal. From this phase difference, the phase and frequency of the clock is modified in order the clock samples the input data at the correct time (in the middle of the bit).


    Classical CDR


    This kind of CDR systems requires that all circuit blocks run at full rate. As a consequence, all circuits in a 40 Gbit/s CDR must operate at 40 GHz, which is not possible in CMOS.
    Another approach compares the phase of the recovered data (Rx Data) with the phase of the receive clock.


    Highscore CDR


    For the edge detection, we need three parallel sampling latches. Two of these latches sample the data and the third is used to sample the edge between the data.


    Half Rate CDR


    In this architecture, each latch must sample every other data bit only. Hence, the clock frequency can be half the input data rate. It is therefore a half-rate architecture. Using even more parallel latches, the clock frequency can further be reduced at the cost of circuit complexity. Actually, we would only need the data bits. But in order to obtain information about the phase relation between the sample phases and the input data, we also need a sample on the edge of the data bits.


    Eary and late clock recovery


    When two consecutive bits have different values, the edge bit can be used to decide if the sample point is correct or if it is too early or too late. If the mean value of all edge samples is 0.5, the sample point is correct. Is the edge sample equal to the preceding bit, the clock samples too early and if the edge and the following bits are equal, the clock samples too late. This leads to logical equation, the Alexander equations:


    Alexander Equation


    Using the information of the early and late bits, the phase of the sample clock will be adjusted until the sample time is correct. In order to adjust the phase of sample clock, a voltage controlled oscillator can be used.


    VCO Equation


    In the VCO, the phase is controlled by the integration of the change of the frequency. This integration can lead to stability problems. Furthermore, when integrating several CDR circuits on one chip, the VCO is not suitable due the required passive components for an oscillator with low phase noise. Passive components are not desired in integrated circuits. The other solution is to directly control the phases of the sampling clock signals by a phase rotator.


    Basic Phase Rotator


    Using the phase rotator, no integrating element is introduced by the phase control circuit. Furthermore, the oscillator which should have a low phase noise is outside of the CDR control loop. Hence, this oscillator can be used for several CDR circuits and therefore mitigates the problem of the on-chip passive components. Moreover, when this oscillator is locked to a stable (low speed) oscillator, the phase-noise requirements decrease and e.g. a ring oscillator, having no passive components, can be employed. In addition, the ring oscillator generates the multiple phases which are needed.

    Based on all the above considerations, the architecture used in the HIGHSCORE-Project was built up.

    Contact : Dr. Alex Huber, IME

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