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      Motivation

      Contents

      Facts
        • Computation speed of the microprocessors or integrated circuits (IC) increases in general permanently
        • The ICs in a system must exchange a larger amount of data
        • Data communication speed between these chips becomes the limiting factor of the overall system performance
      Parallel communication between two chips

      Concept : Parallel Bus Architecture
        • Traditionally, data between two chips are transferred in parallel
      Parrallel data communication between two chips
        • Parallel data D0...Dn are synchronous to single clock Clk
        • Clock/data skew, clock- and data jitter and cross-talk limit the maximum clock frequency fdata and/or the maximum length lmax
      Practical limitations:
        • fClk < 166 MHz, n=16 bit ->  data throughput is 330 MByte/s
        • lmax < 0.5...1 m
      This is a REAL bottleneck. To increase the transfer you may use more parallel data lines and introduce amplitude modulation but based on this concept you may not achieve transfer rate of 40 GByte/s or more.
      Solution : Serial Bus Architecture
      Use a serial bus architectures. This trend, away from parallel buses towards serial architectures, is observed in the computer market for workstations, servers, and gaming stations, where a high data throughput is needed. Serial lines operate at much higher clock rates.

      Bus architecture clock rates

      As the clock frequencies of the microprocessors peripheral chips continuously increase, the amount of data which will be transmitted between the chips will become larger in the future.

      Multiple channel data transfer rates


      It is expected that the today’s speed of one link of 2.5 Gbit/s will increase up to 40 Gbit/s in the next five to ten years. The development of such a link is the goal of our HIGHSCORE project.

      Contact : Dr. Alex Huber, IME
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