Document Actions

    Serial Bus Architecture

    In a serial bus architecture, n parallel data bits are multiplexed (MUX) on the transmitter side. The data transfer takes place at a speed which n-times higher than the data rate of the parallel data. On the receiver side, the data have to be demultiplexed (DEMUX) to reduce the data rate which appropriate for further processing on the chip.


    Serial Data Link

    Why is it possible to achieve higher data rates using serial data buses instead of parallel ones?

      • Data D0...Dn are mutiplexed to one stream
        ⇒ Decision and demultiplexing in the receiver
        ⇒ no data skew
      • Clock signal is not transmitted
        ⇒ Clock recovery in the receiver
        ⇒ no clock skew
      • One clock recovery per link = one clock per link
        ⇒ Link capacity can be linearly scaled
      • Optical transmission (laser, fiber, photodiode) can be employed
        ⇒ unlimited l max

    Contact : Dr. Alex Huber, IME

    Information for: