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    An optimized CPU architecture for cryptological functions

    Summary

    Implementation and analysis of cryptographical primitives on the MicroCore CPU, which has a Forth like assembler language. A C to MicroCore assembler compiler will be developed based on lcc, which is used then to compile the cryptographical primitives  for analysis. In the analysis the expensive steps will be located and then when possible be realised as single cycle instruction for the MicroCore. The MicroCore CPU allows it to implement user defined instructions in VHDL which then are  synthesized into Hardware.

    Keywords

    Post quantum cryptography, Hash function, Merkle authentification trees, MicroCore, Forth, Compiler, VHDL 

    Goals
    1. Identify inner loops in the Forth code of the crypto algorithms, which are potential candidates for direct hardware realisation.
    2. Analyse whether these inner loops can be realised as a single cycle instruction  and translate them into VHDL.
    3. Develop a C-Compiler based on lcc that produces MicroCore Forth native instructions.

    SFW 308 - MicroCore.JPG

    MicroCore development board

    Background

    A general characteristic of most cryptographical algorithms is the repetitive usage of a small set of functions. Their efficient implementation determines how much time and space overhead the security scheme imposes on sending messages between two end points. In a market where pervasive computing on smaller and smaller scales is the rule, the efficiency of this  time/space tradeoff is crucial to guarantee user acceptance and device scalability.

    The unique architecture of MicroCore offers three big advantages in such a market:

    1. Almost a one-to-one conversion between the high level (Forth) specification of the algorithm and its compiled form. This means that a robust and secure implementation at the high level will not degrade through the compilation process.

    2. The possibility to expand the native instruction set without changing the CPU architecture.

    3. The possibility to implement these new instructions directly in hardware through the translation of Forth code into VHDL

    Project information

    Duration: September 2012 - January 2014
    Funding: Hasler Stiftung

    Further information

    - Project Merkle Tree

    Contact

    Prof. Dr. Carlo Nicola
    Tel: +41 56 202 78 26 (Direkt)
    E-Mail: carlo.nicola@fhnw.ch

    Project team

    Carlo Nicola (PL), Willi Meier (IAST), Markus Knecht

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